Publication List

Journal Papers

• Takuya Betchaku, Shuichi Ichikawa: "Reducing wind direction data for the unpredictable random number generator based on linear feedback shift register," IEEJ Transactions on Industry Applications, vol. 145, no. 4, (accepted) (2025). (in Japanese)
• Shuichi Ichikawa: "Random Number Generation from Image Data and LFSR," IEEJ Transactions on Industry Applications, vol. 145, no. 4, (to appear) (2025). (in Japanese)
• Shunsuke Matsuoka, Hideki Kawaguchi, Shuichi Ichikawa: "Expansion of pointing range using phase shift array for ultrasonic positioning system," J. Jpn. Soc. Appl. Electromagn. Mech., vol.32, no.2, pp. 480--485 (2024). (in Japanese) [DOI]
• Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe: "Design and implementation of an on-line quality control system for latch-based true random number generator," IEICE Transactions on Information and Systems, vol. E106-D, no.12, pp.1940-1950 (2023). [1.78MB PDF, copyright © 2023 IEICE] [DOI] [IEICE Transactions]
• Hiroto Kamogari, Shuichi Ichikawa: "Evaluation of a random number generator based on an internal linear feedback shift register," IEEJ Transactions on Industry Applications, vol. 143, no. 2, pp. 87--93 (2023). (in Japanese) [DOI] [704 KB PDF, copyright © 2023 IEEJ]
• Ayumu Chiba, Shuichi Ichikawa: "Evaluation of Random Number Generator Utilizing Weather Data and LFSR," IEEJ Transactions on Industry Applications, vol. 143, no. 2, pp. 80--86 (2023). (in Japanese) [DOI] [672 KB PDF, copyright © 2023 IEEJ]
• Kazuki Iwahara, Shuichi Ichikawa, Naoki Fujieda: "Evaluation of special instruction implementations in soft processors for high-level synthesis," IEEJ Transactions on Industry Applications, vol. 143, no. 2, pp. 94--100 (2023). (in Japanese) [DOI] [800 KB PDF, copyright © 2023 IEEJ]
• Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda: "A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC)," International Journal of Circuit Theory and Applications, vol. 49, no. 10, pp. 3354-3367 (2021). [DOI] [Sharable Link]
• Hidetaka Masaoka, Shuichi Ichikawa, Naoki Fujieda: "Random Number Generation from Internal LFSR and Fluctuation of Sampling Interval," IEEJ Transactions on Industry Applications, vol. 141, no. 2, pp. 86--92 (2021). (in Japanese) [DOI] [738 KB PDF, copyright © 2021 IEEJ]
• Seiya Ogido, Shuichi Ichikawa, Naoki Fujieda, Chikatoshi Yamada, Kei Miyagi: "Experimental Implementation of Fault Tolerance Using Dynamic Partial Reconfiguration on Xilinx Zynq-7000 SoC," IEEJ Transactions on Industry Applications, vol. 141, no. 2, pp. 93--99 (2021). (in Japanese) [DOI] [993 KB PDF, copyright © 2021 IEEJ]
• Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa: "An Analysis of DCM-based True Random Number Generator," IEEE Trans. Circuits and Systems II: Express Briefs, vol. 67, no. 6, pp. 1109--1113 (2020). [DOI] [postprint, copyright © 2019 IEEE]
• Akihiro Yoza, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa, Naoki Fujieda: "Determination of Optimal Parameters for Bilateral Filter for Medical Images," IEEJ Transactions on Electronics, Information and Systems, vol. 139, no. 9, pp. 1008--1014 (2019). (in Japanese) [5655 KB PDF, copyright © 2019 IEEJ] [DOI]
• Tsugushi Nagahama, Ichirou Uehara, Kei Miyagi, Chikatoshi Yamada, Shuichi Ichikawa: "Real-time Inference of Ryukyuan Classical Music Using Deep Learning," IEEJ Transactions on Electronics, Information and Systems, vol. 139, no. 9, pp. 1001--1007 (2019). (in Japanese) [1063 KB PDF, copyright © 2019 IEEJ] [DOI]
• Shotaro Yamada, Shuichi Ichikawa, Naoki Fujieda: "Implementation of Obfuscated Control Logic Circuit with LegUp and oLLVM," IEEJ Transactions on Electronics, Information and Systems, vol. 139, no. 9, pp. 952--957 (2019). (in Japanese) [870 KB PDF, copyright © 2019 IEEJ] [DOI]
• Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa, Naoki Fujieda: "Research on Fault Tolerant Processor using Dynamic Reconfiguration," IEEJ Transactions on Industry Applications, vol. 139, no. 2, pp. 187--192 (2019). (in Japanese) [2272 KB PDF, copyright © 2019 IEEJ] [DOI]
• Yuki Matsuda, Kei Miyagi, Chikatoshi Yamada, Shoichi Tanifuji, Shuichi Ichikawa: "FPGA Implementation of Undersea Video Transmission System for Visible Light Communication," IEEJ Transactions on Industry Applications, vol. 139, no. 2, pp. 180--186 (2019). (in Japanese) [1856 KB PDF, copyright © 2019 IEEJ] [DOI]
• Yuumi Matsuoka, Naoki Fujieda, Shuichi Ichikawa: "Evaluation of hardware obfuscation techniques using obfuscation tool oLLVM," IEEJ Transactions on Industry Applications, vol. 139, no. 2, pp. 111--118 (2019). (in Japanese) [928 KB PDF, copyright © 2019 IEEJ] [DOI]
• Shintaro Nishiwaki, Naoki Fujieda, Shuichi Ichikawa: "Performance evaluation of parallel SAT solver on Xeon Phi processor," IEEJ Transactions on Industry Applications, vol. 139, no. 2, pp. 119--126 (2019). (in Japanese) [768 KB PDF, copyright © 2019 IEEJ] [DOI]
• Taiki Makishi, Shuichi Ichikawa, Naoki Fujieda, Chikatoshi Yamada, Kei Miyagi: "Improved Parameter Estimation Method for Bilateral Filter with Distribution Distance," IEEJ Transactions on Industry Applications, vol. 139, no. 2, pp. 104--110 (2019). (in Japanese) [1280 KB PDF, copyright © 2019 IEEJ] [DOI]
• Naoki Fujieda, Shuichi Ichikawa: "A Latch-latch Composition of Metastability-based True Random Number Generator for Xilinx FPGAs," IEICE Electronics Express (ELEX), Vol. 15, No. 10, pp. 1--12 (2018). [1496KB PDF, copyright © 2018 IEICE] [DOI] [ELEX] [IEICE Transactions]
• Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa: "Evaluation of Register Number Abstraction for Enhanced Instruction Register Files," IEICE Transactions on Information and Systems, Vol. E101-D, No. 6, pp. 1521--1531 (2018). [1.25MB PDF, copyright © 2018 IEICE] [DOI] [IEICE Transactions]
• Naoki Fujieda, Takumi Shinohara, Shuichi Ichikawa, Yuhki Sakaguchi, Shunsuke Matsuoka, and Hideki Kawaguchi: "Attenuation Model for Error Correction of Ultrasonic Positioning System," IEEJ Journal of Industry Applications, Vol. 7, No. 2, pp. 181--188 (2018). [1056 KB PDF, copyright © 2018 IEEJ] [DOI]
• Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa: "A Virtual Cache for Overlapped Memory Accesses of Path ORAM," International Journal of Networking and Computing, vol. 7, no. 2, pp. 106--123 (2017). [Download PDF] [IJNC]
• Taiki Makishi, Shuichi Ichikawa, Naoki Fujieda, Chikatoshi Yamada: "Sub-optimal Parameter Estimation for Bilateral Filter Using Distribution Distance," IEEJ Transactions on Industry Applications, vol. 137, no. 7, pp. 576--582 (2017). (in Japanese) [992 KB PDF, copyright © 2017 IEEJ] [DOI]
• Jin Okaze, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa: "Accelerating Techniques for Sequence Alignment based on an Extended NW Algorithm," IEEJ Transactions on Industry Applications, vol. 136, no. 10, pp. 686--691 (2016). (in Japanese) [1152 KB PDF, copyright © 2016 IEEJ] [DOI]
• Shuto Higa, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa: "Improvement in Look-ahead Matching Hardware for Regular Expression," IEEJ Transactions on Industry Applications, vol. 136, no. 10, pp. 692--697 (2016). (in Japanese) [1024 KB PDF, copyright © 2016 IEEJ] [DOI]
• Takuto Omine, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa: "Security Analysis of Quantum Key Distribution Protocol," IEEJ Transactions on Industry Applications, vol. 136, no. 10, pp. 698--702 (2016). (in Japanese) [800 KB PDF, copyright © 2016 IEEJ] [DOI]
• Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa: "Design and Implementation of Instruction Indirection for Embedded Software Obfuscation," Microprocessors and Microsystems, Vol. 45, Part A, pp. 115--128 (2016). [DOI] [postprint]
• Shinichiro Miura, Shuichi Ichikawa, Naoki Fujieda, Kazuhiko Kakuda: "Performance of sparse matrix-vector multiplication for compressed diagonal storage format using the Intel MIC," Transactions of the Society for Mathematical Sciences, vol.17, no.1, pp.3--8 (2016). (in Japanese)
• Shunsuke Matsuoka, Naoki Fujieda, Shuichi Ichikawa, Hideki Kawaguchi: "Development of Real-time Positioning System by Ultrasonic Waves," J. Jpn. Soc. Appl. Electromagn. Mech., vol.23, no.2, pp.380--385 (2015). [DOI] (in Japanese)
• Naoki Fujieda, Shuichi Ichikawa: "An XOR-based Parameterization for Instruction Register Files," IEEJ Transactions on Electrical and Electronic Engineering, vol. 10, no. 5, pp. 592--602 (2015). [DOI] [preprint]
• Taiki Makishi, Chikatoshi Yamada, Tadashi Ogino, Shuichi Ichikawa: "A study on Estimation Parameter of Bilateral Filter Using Distribution Distance," IEEJ Transactions on Industry Applications, vol. 135, no. 2, pp. 87--92 (2015). (in Japanese) [2624KB PDF, copyright © 2015 IEEJ] [DOI link]
• Fumiya Sadoyama, Chikatoshi Yamada, Shuichi Ichikawa, Tadashi Ogino: "A study on Single Frame Reconstruction-based Super Resolution," IEEJ Transactions on Industry Applications, vol. 135, no. 2, pp. 81--86 (2015). (in Japanese) [1984KB PDF, copyright © 2015 IEEJ] [DOI link]
• Hisashi Hata, Shuichi Ichikawa: "FPGA Implementation of Metastability-based True Random Number Generator," IEICE Transactions on Information and Systems, Vol. E95-D, No. 2, pp. 426--436 (2012). [708KB PDF, copyright © 2012 IEICE] [DOI link] [abstract and PDF from IEICE] [IEICE Transactions]
• Shunsuke Matsuoka, Yoshiki Hino, Shuichi Ichikawa: "Hardware Specialization for Key Specific AES and Camellia Cipher Circuit," IEICE Transactions on Information and Systems (Japanese Edition), [1.79MB PDF, copyright © 2011 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
• Shuichi Ichikawa, Masanori Akinaka, Hisashi Hata, Ryo Ikeda, Hiroshi Yamamoto: "An FPGA implementation of hard-wired sequence control system based on PLC software," IEEJ Transactions on Electrical and Electronic Engineering, Vol. 6, No. 4, pp. 367--375 (2011). [DOI link] [IEEJ Transactions on Electrical and Electronic Engineering] [preprint]
• Shuichi Ichikawa, Sho Takahashi, Yuu Kawai: "Optimizing Process Allocation of Parallel Programs for Heterogeneous Clusters," Concurrency and Computation: Practice and Experience, Vol. 21, No. 4, pp. 475--507 (2009). [DOI link] [Concurrency and Computation: Practice and Experience] [preprint]
• Shuichi Ichikawa, Takashi Sawada, Hisashi Hata: "Diversification of Processors Based on Redundancy in Instruction Set," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No.1, pp. 211--220 (2008). [243KB PDF, copyright © 2008 IEICE] [DOI link] [abstract and PDF from IEICE] [IEICE Transactions]
• Ryoichiro Atono, Shuichi Ichikawa: "Design and Evaluation of Data-dependent Hardware for AES Encryption Algorithm," IEICE Transactions on Information and Systems, Vol. E89-D, No.7, pp. 2301--2305 (2006). [118KB PDF, copyright © 2006 IEICE] [DOI link] [abstract and PDF from IEICE] [IEICE Transactions]
• Kazuhiro Hattanda, Shuichi Ichikawa: "Redundancy in Instruction Sequences of Computer Programs," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 1, pp. 219--221 (2006). [168KB PDF, copyright © 2006 IEICE] [DOI link] [abstract and PDF from IEICE] [IEICE Transactions]
• Shiro Konuma, Shuichi Ichikawa: "Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937," IEICE Transactions on Information and Systems, Vol. E88-D, No. 12, pp. 2876--2879 (2005). [106KB PDF, copyright © 2005 IEICE] [DOI link] [abstract and PDF from IEICE] [IEICE Transactions]
• Yoshinori Kishimoto, Shuichi Ichikawa: "Optimizing the Configuration of a Heterogeneous Cluster with Multiprocessing and Execution-Time Estimation," Parallel Computing, Vol. 31, No. 7, pp. 691--710 (2005). [DOI link] [Parallel Computing] [preprint]
• Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto: "The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem," IEICE Transactions on Information and Systems, Vol. E87-D, No. 8, pp. 2038--2047 (2004). [473KB PDF, copyright © 2004 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
• Kazuhiro Hattanda, Shuichi Ichikawa: "The Evaluation of Davidson's Digital Signature Scheme," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 1, pp. 224--225 (2004). [153KB PDF, copyright © 2004 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
• Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi: "Trade-offs in Custom Circuit Designs for Subgraph Isomorphism Problem," IEICE Transactions on Information and Systems, Vol. E86-D, No. 7, pp. 1250--1257 (2003). [329KB PDF, copyright © 2003 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
• Shuichi Ichikawa, Shoji Yamamoto: "Data Dependent Circuit for Subgraph Isomorphism Problem," IEICE Transactions on Information and Systems, Vol. E86-D, No. 5, pp. 796--802 (2003). [261KB PDF, copyright © 2003 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
• Shuichi Ichikawa, Hiroshi Chiyama, Kazuhiko Akabane: "Redundancy in 3D Polygon Models and Its Application to Digital Signature," Journal of WSCG, Vol. 10, No. 1, pp. 225--232 (2002). (Special Issue WSCG 2002 - FULL papers - 10th Int'l Conf. Central Europe on Computer Graphics, Visualization and Computer Vision 2002) [abstract] [download 107KB PDF] [WSCG]
• Shuichi Ichikawa, Shinji Yamashita: "Static Load-balancing for Distributed Processing of Numerical Simulations," IPSJ Journal, Vol. 42, No. 3, pp. 552--564 (2001). (in Japanese) [352KB PDF] [IPSJ Copyright Notice] [CiNii]
• Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi: "An FPGA-Based Implementation of Subgraph Isomorphism Algorithm," IPSJ Transactions on High Performance Computing Systems, Vol. 41, No. SIG5 (HPS1), pp. 39--49 (2000). (in Japanese) [728KB PDF] [IPSJ Copyright Notice] [CiNii]
• Shuichi Ichikawa, Takamitsu Kawai, Toshio Shimada: "Static Load Balancing for Parallel Numerical Simulation by Combinatorial Optimization," Transactions of Information Processing Society of Japan, Vol. 39, No. 6, pp. 1746--1756 (1998). (in Japanese) [1416KB PDF] [IPSJ Copyright Notice] [CiNii]
• Takamitsu Kawai, Shuichi Ichikawa, Toshio Shimada: "NSL: High Level Language for Parallel Numerical Simulation," Transactions of Information Processing Society of Japan, Vol.38, No.5, pp.1058--1067 (1997). (in Japanese) [CiNii]
• Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto: "The Evaluation of Range-Checking Addressing Modes and the Architecture of FLATS2," IEICE Transactions D-I, Vol. J74-D-I, No.5, pp. 329--338 (May 1993). (in Japanese) [677KB PDF, copyright © 1991 IEICE] [abstract and PDF from IEICE] [IEICE Transactions]
  • Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto: "Evaluation of Range-Checking Addressing Modes and the Architecture of FLATS2," Systems and Computers in Japan, Vol. 23, No. 10, pp. 1--13 (1992). [DOI link]
• Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa: "Pseudo-Random Rounding for Truncated Multipliers," IEEE Transactions on Computers, Vol. 40, No. 9, pp. 1065--1067 (Sep. 1991). [DOI link]
• Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa: "CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined Machines," IEEE Transactions on Computers, Vol. 38, No. 6, pp. 825--832 (Jun. 1989). [DOI link]

Conference Papers

• Ayumu Chiba, Shuichi Ichikawa: "Random number generation based on cryptocurrency prices and linear feedback shift register," Proc. Twelfth International Symposium on Computing and Networking (CANDAR 2024), (accepted) (2024).
• Shuichi Ichikawa: "Pseudo-Random Number Generation by Staggered Sampling of LFSR," Proc. Eleventh International Symposium on Computing and Networking (CANDAR 2023), pp. 134--140 (2023). [DOI] [preprint]
• I. Uehara, C. Yamada, H. Kamehama, K. Miyagi, S. Ichikawa: "Comparison of Processors for Real-time Homography Transformation," The 1st KOSEN Research International Symposium (KRIS 2023), Poster No. 109 (2023).
• T.Uehara, C. Yamada, H. Kamehama, K. Miyagi, S. Ichikawa: "Hardware implementation of learning super-resolution processing," The 1st KOSEN Research International Symposium (KRIS 2023), Poster No. 37 (2023).
• Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa: "An HLS implementation of on-the-fly randomness test for TRNGs," Proc. Tenth International Symposium on Computing and Networking (CANDAR 2022), pp. 151-157 (2022). (Outstanding Paper Award) [DOI] [preprint]
• Shunsuke Matsuoka, Shuichi Ichikawa: "Verification of True Random Number Generator using AD converter with built in microcomputer and FPGA," 35th Workshop on Circuits and Systems, WIP2-2 (2022).
• Shotaro Yamada, Shuichi Ichikawa: "Netlist-based measures for hardware obfuscation: A preliminary study," Proc. 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW 2020), pp. 116--119 (2020). [DOI]
• Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa: "A light-weight implementation of latch-based true random number generator," Proc. 15th International Wireless Communications & Mobile Computing Conference (IWCMC 2019), pp. 901--906 (2019). [DOI] [postprint]
• Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa: "An Analysis on Randomness of Path ORAM for Light-weight Implementation," Proc. Sixth International Symposium on Computing and Networking Workshops (CANDARW 2018), pp. 163--165 (2018). [DOI]
• Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa: "A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity," Proc. 2018 IEEE Region 10 Conference (TENCON 2018), pp. 1489--1492 (2018). [DOI] [postprint]
• Shingo Takahashi, Shunsuke Matsuoka, Hideki Kawaguchi, Naoki Fujieda, Shuichi Ichikawa: "Distance correction using attenuation of receiver signal for the ultrasonic measurement system," The 37th JSST Annual International Conference on Simulation Technology (JSST 2018), Student session, P09 (2018).
• Hiromichi Itoi, Shunsuke Matsuoka, Hideki Kawaguchi, Naoki Fujieda, Shuichi Ichikawa: "Improvement of the directivity for ultrasonic positionning system by using array transmitters," The 37th JSST Annual International Conference on Simulation Technology (JSST 2018), Student session, P10 (2018).
• Akihiro Yoza, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa: "A Study on the Effective Number of Iterations of Bilateral Filter for Medical Images," The 23rd Intelligent Mechatronics Workshop (IMEC 2018), 1B1-4 (2018). (in Japanese)
• Shotaro Yamada, Shuichi Ichikawa, Naoki Fujieda: "An Experimental Implementation of Obfuscated Control Logic Circuit with LegUp," The 23rd Intelligent Mechatronics Workshop (IMEC 2018), 2B4-2 (2018). (in Japanese)
• Joji Sakamoto, Naoki Fujieda, Shuichi Ichikawa: "Preliminary Implementation of Special Instructions for Custom Processors Generated by High Level Synthesis," 2nd cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2018), Session 5B (2018). (in Japanese)
• Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa: "An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis," Proc. Fifth International Symposium on Computing and Networking (CANDAR 2017), pp. 323--325 (2017). [DOI]
• Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa: "A Study of a Fault-tolerant System Using Dynamic Partial Reconfiguration," Proc. Fifth International Symposium on Computing and Networking (CANDAR 2017), pp. 600--602 (2017). [DOI]
• Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka: "Evaluation of the hardwired sequence control system generated by high-level synthesis," Proc. 26th IEEE International Symposium on Industrial Electronics (ISIE 2017), pp. 1261--1267 (2017). [DOI] [postprint]
• Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa: "Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM," Proc. Fourth International Symposium on Computing and Networking (CANDAR 2016), pp.347--353 (2016). [DOI] [postprint]
• Shunsuke Matsuoka, Naoki Fujieda, Shuichi Ichikawa: "Evaluation of hardware obfuscation of AES circuits by white box cryptography," The 29th Workshop on Circuits and Systems, pp. 25--29 (2016). (in Japanese)
• Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa: "A Complement to Enhanced Instruction Register File against Embedded Software Falsification," Proc. ACM SIGPLAN on Program Protection and Reverse Engineering Workshop 2015 (PPREW'15), Article No. 3, pp. 1--7 (2015). [DOI] [download from ACM]
• Shunsuke Matsuoka, Naoki Fujieda, Shuichi Ichikawa: "S-Box Absorption Design for Key-SpeCific AES circuits," Proc. International Conference of Global Network for Innovative Technology (IGNITE2014), pp. 316--319 (2014).
• Yusuke Ayuzawa, Naoki Fujieda, Shuichi Ichikawa: "Design Trade-offs in SHA-3 Multi-Message Hashing on FPGAs," Proc. IEEE TENCON 2014 (2014). [DOI]
• Taiki Makishi, Shuichi Ichikawa, Tadashi Ogino, Chikatoshi Yamada: "An Efficient Estimation Parameter Method of Bilateral Filter Using Distribution Distance," Proc. IEEE TENCON 2014 (2014). [DOI]
• Naoki Fujieda, Shuichi Ichikawa: "Enhanced Instruction Register Files for Embedded Software Obfuscation," Proceedings of the 29th International Conference on Computers and Their Applications (CATA-2014), pp.153--158 (2014). (Best Paper Award Finalist)
• Naoki Fujieda, Shuichi Ichikawa: "An XOR-based approach to merging entries for instruction register files," Proceedings of First International Symposium on Computing and Networking (CANDAR 2013), pp. 332--337. (2013). [DOI link]
• Shunsuke Matsuoka, Shuichi Ichikawa: "Reduction of Power Consumption in Key-specific AES circuits," Proceedings of the Third International Conference on Networking and Computing (ICNC 2012), pp. 323--325 (2012). [DOI link]
• Satoru Tamura, Chikatoshi Yamada, Shuichi Ichikawa: "Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning," Proceedings of the Third International Conference on Networking and Computing (ICNC 2012), pp. 334--335 (2012). [DOI link]
• Muh Syafiq Irsyadi, Shuichi Ichikawa: "Two Hardware Designs of BLAKE-256 Based on Final Round Tweak," Proceedings of the 2011 IEEE Region 10 Conference (TENCON 2011), pp. 350--354 (2011). [DOI link] [download 180KB PDF © IEEE]
• Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda: "Design and Implementation of Hard-wired Tracking Control System," Proceedings of the 2010 IEEE Region 10 Conference (TENCON 2010), pp. 299--304 (2010). [DOI link] [download 277KB PDF © IEEE]
• Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda: "Evaluation of the Hardware Specialization Techniques for Vibration Control Applications," Proceedings of the IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), pp. 579--584 (2010). [DOI link] [download 206KB PDF © IEEE]
• Shuichi Ichikawa, Shoichiro Takagi: "Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study," Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems (CISIS 2009), pp. 1245--1251 (2009). [DOI link] [Download PDF from IEEE-CS] [download 268KB PDF © IEEE]
• Shuichi Ichikawa, Masayoshi Asakura, Yusuke Sakumoto: "Estimating the Optimal Configuration of a Heterogeneous Cluster: the Case of NAS Parallel Benchmarks," Proceedings of 8th International Conference on Applications and Principles of Information Science (APIS 2009), pp.241--244 (2009). [178KB PDF]
• Shuichi Ichikawa, Yuu Kawai: "Constructing Execution-Time Estimation Models from Diverse Processing Elements of Heterogeneous Clusters," Proceedings of IEEE TENCON 2008, pp. 1--6 (2008). (CDROM) [DOI link] [download 210KB PDF © IEEE]
• Shuichi Ichikawa, Masanori Akinaka, Ryo Ikeda, Hiroshi Yamamoto: "Converting PLC instruction sequence into logic circuit: A preliminary study," Proceedings of 2006 IEEE International Symposium on Industrial Electronics (ISIE '06), pp. 2930--2935 (2006). [DOI link] [download 580KB PDF © IEEE]
• Shuichi Ichikawa, Naohiro Kobayashi: "Preliminary Study of Custom Computing Hardware for the 3x+1 Problem," Proceedings of IEEE TENCON 2004, Vol. D, pp. 387--390 (2004). [DOI link] [download 74KB PDF © IEEE]
• Sho Takahashi, Shuichi Ichikawa: "Preliminary Study of a Real-Time Aberration Correction System for Scanning Transmission Electron Microscopes," Proceedings of SACSIS2004, pp. 127--128 (2004). (in Japanese) [IPSJ Copyright Notice] [82KB PDF]
• Yoshinori Kishimoto, Shuichi Ichikawa: "An Execution-Time Estimation Model for Heterogeneous Clusters," 13th Heterogeneous Computing Workshop (HCW 2004), in Proceedings of 18th International Parallel and Distributed Processing Symposium (IPDPS'04), IEEE Computer Society (2004). (CD-ROM) [DOI link] [download 316KB PDF © IEEE]
• Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto: "Data Dependent Circuit Design: A Case Study," Proceedings of 13th Int'l Conf. on Field Programmable Logic and Applications (FPL 2003), LNCS 2778, Springer, pp. 1024--1027 (2003). [abstract and PDF from Springer] [download 256KB PDF © Springer-Verlag] [LNCS homepage]
• Yoshinori Kishimoto, Shuichi Ichikawa: "The Execution Time Estimation Model for Heterogeneous Clusters and Its Evaluation," Proceedings of SACSIS2003, pp. 167--168 (2003). (in Japanese) [IPSJ Copyright Notice] [98KB PDF]
• Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto: "The Implementation and Evaluation of Data Dependent Hardware for Subgraph Isomorphism Problems," Proceedings of SACSIS2003, pp. 181--182 (2003). (in Japanese) [IPSJ Copyright Notice] [78KB PDF]
• Shuichi Ichikawa, Shoji Yamamoto: "Data Dependent Circuit for Subgraph Isomorphism Problem," Proceedings of 12th Int'l Conf. on Field Programmable Logic and Applications (FPL 2002), LNCS 2438, Springer, pp. 1068--1071 (2002). [abstract and PDF from Springer] [download 80KB PDF © Springer-Verlag] [LNCS homepage]
• Yoshinori Kishimoto, Shuichi Ichikawa: "Parallel Linpack Benchmark Results on Heterogeneous Cluster," Proceedings of JSPP2002, pp. 177--178 (2002). (in Japanese) [IPSJ Copyright Notice] [76KB PDF]
• Shoji Yamamoto, Shuichi Ichikawa: "Data Dependent Hardware for Subgraph Isomorphism Problem," Proceedings of JSPP2002, pp. 175--176 (2002). (in Japanese) [IPSJ Copyright Notice] [83KB PDF]
• Shuichi Ichikawa, Yoshikatsu Fujimura: "Iterative Data Partitioning Scheme of Parallel PDE Solver for Heterogeneous Computing Cluster," Proceedings of IASTED Int'l Conf. Applied Informatics: Int'l Symp. Parallel and Distributed Computing and Networks, ACTA Press, pp. 364--369 (2002). [abstract] [87K pdf]
• Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi: "Evaluation of Accelerator Designs for Subgraph Isomorphism Problem," Proceedings of 10th Int'l Conf. on Field Programmable Logic and Applications (FPL 2000), LNCS 1896, Springer, pp. 729--738 (2000). [abstract] [download 176KB PDF © Springer-Verlag] [abstract and PDF from Springer] [LNCS homepage]
• Shuichi Ichikawa, Shinji Yamashita: "Static Load Balancing of Parallel PDE Solver for Distributed Computing Environment," Proceedings of ISCA 13th Int'l Conf. Parallel and Distributed Computing Systems (PDCS-2000), pp. 399--405 (2000). [abstract] [192KB pdf]
• Yoshikatsu Fujimura, Shuichi Ichikawa: "Iterative Partitioning for Static Load-balancing of Numerical Simulations," Proceedings of JSPP '00, p. 171 (2000). (in Japanese) [IPSJ Copyright Notice] [24K ps.gz] [46K pdf]
• Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi: "Hardware Accelerator for Subgraph Isomorphism Problems," Proceedings of Eighth IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'00), pp. 283--284 (2000). [abstract] [DOI link] [download 140KB PDF © IEEE]
• Shinji Yamashita, Shuichi Ichikawa: "Static load-balancing for distributed processing of numerical simulations," Proceedings of Joint Symposium on Parallel Processing 1999 (JSPP '99), p. 204 (1999). (in Japanese) [IPSJ Copyright Notice] [18K ps.gz] [40K pdf]
• Yoshikatsu Fujimura, Shuichi Ichikawa: "Enhancements on Static Load-balancing Scheme for Parallel Numerical Simulations," Proceedings of Joint Symposium on Parallel Processing 1999 (JSPP '99), p. 203 (1999). (in Japanese) [IPSJ Copyright Notice] [18K ps.gz] [45K pdf]
• Takamitsu Kawai, Shuichi Ichikawa, Toshio Shimada: "NSL: High-Level Language for Parallel Numerical Simulation," Proceedings of the IASTED International Conference Modeling and Simulation (MS '99), pp. 208--213 (1999).
• Shuichi Ichikawa, Takamitsu Kawai, Toshio Shimada: "Enhanced Optimization Scheme for Parallel PDE Solver of NSL," Proceedings of Joint Symposium on Parallel Processing 1998 (JSPP '98), p. 143 (1998). [IPSJ Copyright Notice] [22K ps.gz] [16K pdf]
• Shuichi Ichikawa, Takamitsu Kawai, Toshio Shimada: "Mathematical Programming Approach for Static Load Balancing of Parallel PDE Solver," Proceedings of the 16th IASTED International Conference on Applied Informatics, pp. 112--114 (1998). [44K ps.gz] [40K pdf]
• Shuichi Ichikawa, Toshio Shimada: "Reconfigurable PCI card for Personal Computing," Proceedings of the 5th FPGA/PLD Design Conference & Exhibit, pp. 269--277 (1997). (in Japanese) [160K ps.gz] [120K pdf]
• Takamitsu Kawai, Shuichi Ichikawa, Toshio Shimada: "NSL: Parallel Numerical Simulation Language," Proceedings of '97 RWC Symp. TR-96001, pp.545--546 (1997).
• Takamitsu Kawai, Shuichi Ichikawa, Toshio Shimada: "Research on Parallel Numerical Simulation Language," Proceedings of '95 RWC Symp. TR-95001, pp.109--110 (1995).
• Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto: "Multiple Instruction Streams in a Highly Pipelined Processor," Second IEEE Symp. on Parallel and Distributed Processing, pp. 182--189 (Dec. 1990). [DOI link]
• Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto: "Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking," 16th Int'l Symp. on Computer Architecture, pp. 290--297 (May. 1989). [DOI link]

In Books

• Shuichi Ichikawa, "Embedded Software," Life support robot technology required for the future of the super-aging society (medical, welfare and long-term care and rehabilitation), Johokiko Co., Ltd., Section 5.1, pp. 295--299 (2015). (in Japanese)
• Shuichi Ichikawa: "Custom Computing Machinery for Hard Computation Problems," Algorithm Engineering (K. Sugihara, et al. Ed.), Kyoritsu Shuppan, Section 6.27, pp. 270--271 (2001). (in Japanese)
• H. Aiso (Ed.): Dictionary of Information Technology Terms, Ohm-sha (2001).
• Shuichi Ichikawa, Eiichi Goto: "Evaluation of FLATS2 Instruction Set Architecture," Advances in Quantum Flux Parametron Computer Design (Eiichi Goto, Y. Wada, K. Loe Ed.), World Scientific, pp. 221--238 (1992).
• Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto: "Multiple Instruction Streams in a Highly Pipelined Processor," Advances in Quantum Flux Parametron Computer Design (E. Goto, Y. Wada, K. Loe Ed.), World Scientific, pp. 156--178 (1992).

Doctoral Dissertation

• Shuichi Ichikawa, "A study on a cyclic pipeline computer FLATS2," Doctoral Dissertation, the University of Tokyo (1991). [DOI link]

Others

Technical Reports, SIG proceedings, etc. would be found HERE. (Sorry, but Japanese only)

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